Y. Lou, D. Clark, P. Marks, R. J. Muellerschoen and C. C. Wang, "Onboard Radar Processor Development for Rapid Response to Natural Hazards," in IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing, vol. 9, no. 6, pp. 2770-2776, June 2016.
doi: 10.1109/JSTARS.2016.2558505
Abstract:
The unique capabilities of imaging radar to penetrate cloud cover and collect data in darkness over large areas at high resolution makes it a key information provider for the management and mitigation of natural and human-induced hazards. Researchers have demonstrated the use of UAVSAR data to determine flood extent, forest fire extent, lava flow, and landslide. Data latency of at most 2–3 h is required for the radar data to be of use to the disaster responders. We have developed a UAVSAR on-board processor for real time and autonomous operations that has high fidelity and accuracy to enable timely generation of polarimetric and interferometric data products for rapid response applications. This on-board processor design provides a space-qualification path for technology infusion into future space missions in a high-radiation environment with modest power and weight allocations. The processor employs a hybrid architecture where computations are divided between field-programmable gate arrays, which are better suited to rapid, repetitious computations, and a microprocessor with a floating-point coprocessor that is better suited to the less frequent and irregular
computations. Prior to implementing phase preserving processor algorithms in FPGA code, we developed a bit-true processor model in MATLAB that is modularized and parameterized for ease of testing and the ability to tradeoff processor design with performance. The on-board processor has been demonstrated on UAVSAR flights.
The final OBP, housed in a commercial cPCI chassis, is 17.5 × 43 × 36 cm and weighs 14 kg. For flight testing, it is rack mounted in the cabin of a NASA G-III jet that carries the UAVSAR radar in a pod beneath the fuselage. An optical cable from the radar pod provides formatted radar data to the OBP. Fig. 3 shows an image acquired on one of the flights. The OBP operates in real time, with an initial latency of 50 s. The latency is mainly due to two large buffers used in the processor: one is the large FIFO buffer that allows time for the preprocessor to make computations, and the other is the corner-turn buffer between range and azimuth processing. The average radar data rate to the OBP from the radar is approximately 6.1 MB/s (the rate varies with aircraft speed). When configured like the ground processor (e.g., with no postprocessing), the processor generates a high resolution fully focused patch of 6472 × 3328 complex samples every 8 s, and consumes 68 W of power, of which the FPGA board consumes 23 W. In comparison, the software ground processor running on a high-end desktop computer outputs a patch of similarly processed data approximately every 45 s (or about 1/6 of real time), and consumes 265 W of power. When fully configured with two FPGA boards and the postprocessor, the five-year old OBP consumes 125 W of power, which is expected to be at least 50% lower if new generation FPGAs and μP boards are used. Finally, the average high-resolution output data rate is approximately 16.1 MB/s, which is much too high for most available aircraft downlinks. As previously discussed, the postprocessor reduces the patch size to a user-defined resolution and converts the patches to images; at a typical final image size that we use of 600 KB, the OBP outputs data at approximately 75 KB/s.
keywords:
{Earth;Field programmable gate arrays;Radar imaging;Real-time systems;Software;Synthetic aperture radar;On-board processor (OBP);UAVSAR;rapid response;real-time processing;synthetic aperture radar (SAR)},
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7471399&isnumber=7503125
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